Electroless deposition of Co, Ni, and alloys thereof is employed in a variety of applications in the manufacture of microelectronic devices. For example, it is known to deposit a Co-based cap on interconnect metallization. In particular, in damascene processing, metallization is employed to form electrical interconnects in an integrated circuit substrate by metal-filling of interconnect features such as vias and trenches formed in the substrate.
If metal deposited on an integrated circuit substrate is Cu, it can diffuse rapidly into the Si substrate and dielectric films such as, for example, SiO2 or low k dielectrics. Copper can also diffuse into a device layer built on top of a substrate in multilayer device applications. Such diffusion can be detrimental to the device because it can cause electrical leakage in substrates, or form an unintended electrical connection between two interconnects resulting in an electrical short. Moreover, Cu diffusion out of an interconnect feature can disrupt electrical flow there through.
Metal deposited on an integrated circuit substrate also has a tendency to migrate when electrical current passes through interconnect features in service. Electron flux moves the metal atoms from one place of the interconnect feature, creating the void, and moves them to the different location, forming hillock. This migration can damage an adjacent interconnect line, and disrupt electrical flow in the feature from which the metal migrates.
After metal-filling of interconnect features, chemical mechanical polishing is employed to planarize and smooth the metallization deposited within the interconnect features. See, for example, Dubin et al. (U.S. Pat. No. 5,891,513) (describing CMP).
Accordingly, among the challenges facing integrated circuit device manufacturers is to minimize diffusion and electromigration of metal out of metal-filled interconnect features. This challenge becomes more acute as the devices further miniaturize, and as the features further miniaturize and densify.
Another challenge in the context of metal interconnect features is to protect them from corrosion. Certain interconnect metals, especially Cu, are more susceptible to corrosion.
Copper is a fairly reactive metal which readily oxidizes under ambient conditions. This reactivity can undermine adhesion to dielectrics and thin films, resulting in voids and delamination. Another challenge is therefore to combat oxidation and enhance adhesion between the cap and the Cu, and between structure layers.
To address these challenges the industry has employed a variety of diffusion barrier layers as caps over Cu and other metal interconnect features. Electroless Co and Ni have been discussed as protective layers over electrical interconnect lines in, for example, U.S. patent publication number 2003/0207560.
A particular cobalt-based metal capping layer employed to reduce Cu migration, provide corrosion protection, and enhance adhesion between the dielectric and Cu is a ternary alloy including cobalt, tungsten, and phosphorus. See Dubin et al. (U.S. Pat. No. 5,695,810) (Co—W—P as a barrier material on a semiconductor wafer). Another refractory metal may replace or be used in addition to tungsten, and boron is often substituted for or used in addition to phosphorus. Each component of the ternary alloy imparts advantages to the protective layer.
A particular problem associated with diffusion barrier layers is roughness of the layer surface. Roughness can entrap contaminants during wet processing, cause defects and voids thereby promoting electromigration failure, affect the signal propagation across the circuitry, and promote nodular, dendritic growth of the electroless deposit at the barrier/Cu interface, which can significantly reduce selectivity of the capping layer, increase current leakage, and in extreme cases even result in electrical shorts.
Generally, electroless deposition solutions deposit a capping layer that amplifies roughness of the underlying copper interconnect topography, giving a rough, nodular deposit in the capping layer. Although CMP is often performed on the Cu interconnect features, some roughness persists on the Cu surface, which is then amplified by the cap.
Therefore, there exists a need for smoother electrolessly deposited capping layers over Cu interconnects. There is a particular need for an electroless deposition method and solution which can improve the topography and morphology of an electroless deposit and result in a significantly smoother electroless layer.